1. Field of the Invention
The present invention relates to a process for the manufacture of power-MOS semiconductor devices with high density of the elementary MOS cells.
2. Description of the Prior Art
In the manufacture of power-MOS devices there are commonly used techniques aimed at the embodiment of high cell density typical of Large Scale Integration (LSI) technology which allow the integration of numerous cells of the device and structures with ever smaller characteristic dimensions, i.e. with smaller silicon areas, or with better performances for a given silicon area used. The present density of power-MOS devices is on the order of 2-3 million elementary cells per square inch, to which corresponds for the elementary cell a typical "Xpitch" dimension of approximately 17 .mu.m where Xpitch stands for (see FIG. 1) the sum of the side dimension Xd (approximately 7 .mu.m) of the gate electrode, and of the dimension Xc (approximately 10 .mu.m) of the opening in the polycrystalline silicon layer.
The minimum dimensions of the cell obtained in accordance with conventional processes are conditioned by the resolving power and the alignment limits of the photographic exposure system used, as well as the tolerances imposed by the various steps of the production process. More precisely, the minimal dimensions Xc are determined by the requirement to effect three successive alignments inside the polycrystalline silicon, and by the technological limit associated with the smallest possible openings. Using conventional photographic exposure equipment with projection the minimal dimensions of Xc are approximately 8 .mu.m.
The smallest side dimensions of the gate (Xd) are linked to the requirement of allowing sufficiently deep diffusion of the body dopant to prevent the formation of short circuits due to the so-called spikes of aluminum which occur in conventional metallizations. Said minimal dimensions of Xd are approximately 6-7 .mu.m regardless of the technique used.